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| author | Carl Ritson <carl.ritson@amd.com> | 2018-09-19 16:32:12 +0000 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2018-09-19 16:32:12 +0000 |
| commit | 6b8d75425eebee8c0c2b279ac2cf0c669d1846fe (patch) | |
| tree | b280f08263b18d8b2bcd71e86a7586d984cdb68c /llvm/lib | |
| parent | 6183c6316d2187a4cbca23e7c3e07d36ef1edd8b (diff) | |
| download | bcm5719-llvm-6b8d75425eebee8c0c2b279ac2cf0c669d1846fe.tar.gz bcm5719-llvm-6b8d75425eebee8c0c2b279ac2cf0c669d1846fe.zip | |
[AMDGPU] Add instruction selection for i1 to f16 conversion
Summary:
This is required for GPUs with 16 bit instructions where f16 is a
legal register type and hence int_to_fp i1 to f16 is not lowered
by legalizing.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52018
Change-Id: Ie4c0fd6ced7cf10ad612023c6879724d9ded5851
llvm-svn: 342558
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index ee545e012c9..8695b16a8da 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1321,6 +1321,16 @@ def : GCNPat < >; def : GCNPat < + (f16 (sint_to_fp i1:$src)), + (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src)) +>; + +def : GCNPat < + (f16 (uint_to_fp i1:$src)), + (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_ONE), $src)) +>; + +def : GCNPat < (f32 (sint_to_fp i1:$src)), (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src) >; |
