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author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-23 21:40:39 +0000 |
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committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-23 21:40:39 +0000 |
commit | 6a7f02082b800bce4fc2e37a3ad50279abc3a663 (patch) | |
tree | 99a38f00f092e2f3cd823ef4be6f30afd4a5b4d8 /llvm/lib | |
parent | 33b0d85f6544e6ac6293c34e99244cbabda6771b (diff) | |
download | bcm5719-llvm-6a7f02082b800bce4fc2e37a3ad50279abc3a663.tar.gz bcm5719-llvm-6a7f02082b800bce4fc2e37a3ad50279abc3a663.zip |
Corrected a bug in SparcRegInfo.cpp - to add inserted instructions before a return
llvm-svn: 969
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcRegClassInfo.h | 2 | ||||
-rw-r--r-- | llvm/lib/Target/Sparc/SparcRegInfo.cpp | 31 |
2 files changed, 16 insertions, 17 deletions
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h index 311d035c296..4f91268c374 100644 --- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h +++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h @@ -66,7 +66,7 @@ class SparcIntRegOrder{ }; // max # of colors reg coloring can allocate - static unsigned int const NumOfAvailRegs = g0; + static unsigned int const NumOfAvailRegs = i6; static unsigned int const StartOfNonVolatileRegs = l0; static unsigned int const StartOfAllRegs = o0; diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp index b28ce51b989..0f3f9dc1bba 100644 --- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp @@ -621,8 +621,7 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI, assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) ); - - suggestReg4RetAddr(RetMI, LRI); + suggestReg4RetAddr(RetMI, LRI); // if there is an implicit ref, that has to be the ret value if( RetMI->getNumImplicitRefs() > 0 ) { @@ -681,37 +680,37 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI, unsigned RegClassID = getRegClassIDOfValue(RetVal); unsigned RegType = getRegType( RetVal ); - unsigned UniRetReg = InvalidRegNum; - + + + unsigned CorrectCol; if(RegClassID == IntRegClassID) - UniRetReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 ); + CorrectCol = SparcIntRegOrder::i0; else if(RegClassID == FloatRegClassID) - UniRetReg = getUnifiedRegNum( RegClassID, SparcFloatRegOrder::f0); - + CorrectCol = SparcFloatRegOrder::f0; + else + assert( 0 && "Unknown RegClass"); // if the LR received the suggested color, NOTHING to do if( LR->hasSuggestedColor() && LR->hasColor() ) if( LR->getSuggestedColor() == LR->getColor() ) - return; + if( LR->getColor() == CorrectCol ) + return; + + unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol ); if( LR->hasColor() ) { - // We are here because the LR was allocted a regiter, but NOT - // the correct register. + // We are here because the LR was allocted a regiter + // It may be the suggested register or not // copy the LR of retun value to i0 or f0 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor()); - if(RegClassID == IntRegClassID) - UniRetReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0); - else if(RegClassID == FloatRegClassID) - UniRetReg = getUnifiedRegNum( RegClassID, SparcFloatRegOrder::f0); - AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType); - + RetAI->InstrnsBefore.push_back( AdMI ); } else assert(0 && "TODO: Copy the return value from stack\n"); |