[GlobalISel][X86] Support G_BRCOND operation.

Summary: Support G_BRCOND operation. For now don't try to fold cmp/trunc instructions.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34754

llvm-svn: 311327

2 files changed, 33 insertions, 0 deletions

diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index c29f402b522..8902d7bfcda 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -83,6 +83,8 @@ private:
                     MachineFunction &MF) const;
   bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
                      MachineFunction &MF) const;
+  bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
+                        MachineFunction &MF) const;
 
   // emit insert subreg instruction and insert it before MachineInstr &I
   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
@@ -330,6 +332,8 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
     return true;
   if (selectInsert(I, MRI, MF))
     return true;
+  if (selectCondBranch(I, MRI, MF))
+    return true;
 
   return false;
 }
@@ -1101,6 +1105,29 @@ bool X86InstructionSelector::selectMergeValues(MachineInstr &I,
   I.eraseFromParent();
   return true;
 }
+
+bool X86InstructionSelector::selectCondBranch(MachineInstr &I,
+                                              MachineRegisterInfo &MRI,
+                                              MachineFunction &MF) const {
+  if (I.getOpcode() != TargetOpcode::G_BRCOND)
+    return false;
+
+  const unsigned CondReg = I.getOperand(0).getReg();
+  MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
+
+  MachineInstr &TestInst =
+      *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
+           .addReg(CondReg)
+           .addImm(1);
+  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1))
+      .addMBB(DestMBB);
+
+  constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
+
+  I.eraseFromParent();
+  return true;
+}
+
 InstructionSelector *
 llvm::createX86InstructionSelector(const X86TargetMachine &TM,
                                    X86Subtarget &Subtarget,
diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index b1075995be2..05fde0fb92d 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -80,6 +80,9 @@ void X86LegalizerInfo::setLegalizerInfo32bit() {
   for (auto Ty : {s1, s8, s16})
     setAction({G_GEP, 1, Ty}, WidenScalar);
 
+  // Control-flow
+  setAction({G_BRCOND, s1}, Legal);
+
   // Constants
   for (auto Ty : {s8, s16, s32, p0})
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
@@ -141,6 +144,9 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
   for (auto Ty : {s1, s8, s16})
     setAction({G_GEP, 1, Ty}, WidenScalar);
 
+  // Control-flow
+  setAction({G_BRCOND, s1}, Legal);
+
   // Constants
   for (auto Ty : {s8, s16, s32, s64, p0})
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);