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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-04-20 15:58:46 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-04-20 15:58:46 +0000 |
| commit | 6779075c441b49304ba27d4a7373eaa0babb94f7 (patch) | |
| tree | e79b9c128a2269a2afd4633642d182dd32bd32a4 /llvm/lib | |
| parent | 1962f709c700cc33ed26549092475f5ba72a608f (diff) | |
| download | bcm5719-llvm-6779075c441b49304ba27d4a7373eaa0babb94f7.tar.gz bcm5719-llvm-6779075c441b49304ba27d4a7373eaa0babb94f7.zip | |
[PowerPC] Flow oversized lines for r235309
llvm-svn: 235310
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/README_ALTIVEC.txt | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/llvm/lib/Target/PowerPC/README_ALTIVEC.txt b/llvm/lib/Target/PowerPC/README_ALTIVEC.txt index e40c44b8272..f70ebd82bd5 100644 --- a/llvm/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/llvm/lib/Target/PowerPC/README_ALTIVEC.txt @@ -316,14 +316,28 @@ a single target type. This should probably be addressed in the PPCISelDAGToDAG //===----------------------------------------------------------------------===// -Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only for v2f64 with VSX available. We should create custom lowering support for the other vector types. Without this support, we generate sequences with load-hit-store hazards. - -v4f32 can be supported with VSX by shifting the correct element into big-endian lane 0, using xscvspdpn to produce a double-precision representation of the single-precision value in big-endian double-precision lane 0, and reinterpreting lane 0 as an FPR or vector-scalar register. - -v2i64 can be supported with VSX and P8Vector in the same manner as v2f64, followed by a direct move to a GPR. - -v4i32 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 1, using a direct move to a GPR, and sign-extending the 32-bit result to 64 bits. - -v8i16 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 3, using a direct move to a GPR, and sign-extending the 16-bit result to 64 bits. - -v16i8 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 7, using a direct move to a GPR, and sign-extending the 8-bit result to 64 bits. +Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only +for v2f64 with VSX available. We should create custom lowering +support for the other vector types. Without this support, we generate +sequences with load-hit-store hazards. + +v4f32 can be supported with VSX by shifting the correct element into +big-endian lane 0, using xscvspdpn to produce a double-precision +representation of the single-precision value in big-endian +double-precision lane 0, and reinterpreting lane 0 as an FPR or +vector-scalar register. + +v2i64 can be supported with VSX and P8Vector in the same manner as +v2f64, followed by a direct move to a GPR. + +v4i32 can be supported with VSX and P8Vector by shifting the correct +element into big-endian lane 1, using a direct move to a GPR, and +sign-extending the 32-bit result to 64 bits. + +v8i16 can be supported with VSX and P8Vector by shifting the correct +element into big-endian lane 3, using a direct move to a GPR, and +sign-extending the 16-bit result to 64 bits. + +v16i8 can be supported with VSX and P8Vector by shifting the correct +element into big-endian lane 7, using a direct move to a GPR, and +sign-extending the 8-bit result to 64 bits. |
