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| author | Lei Huang <lei@ca.ibm.com> | 2018-07-05 07:46:01 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-07-05 07:46:01 +0000 |
| commit | 66e22c21c316cadb6023268273d29534d148a54d (patch) | |
| tree | 1bb80f45a5d059fdd14b52862fb5684fb2663d4e /llvm/lib | |
| parent | 350c5f1881a8387119545a90daced0e6cce1165d (diff) | |
| download | bcm5719-llvm-66e22c21c316cadb6023268273d29534d148a54d.tar.gz bcm5719-llvm-66e22c21c316cadb6023268273d29534d148a54d.zip | |
[Power9] Optimize codgen for conversions of int to float128
Optimize code sequences for integer conversion to fp128 when the integer is a result of:
* float->int
* float->long
* double->int
* double->long
Differential Revision: https://reviews.llvm.org/D48429
llvm-svn: 336316
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 06e06404a18..3bdf9d8737a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2548,9 +2548,16 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; def : Pat<(f128 (sint_to_fp i64:$src)), (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; + def : Pat<(f128 (sint_to_fp (i64 (PPCmfvsr f64:$src)))), + (f128 (XSCVSDQP $src))>; + def : Pat<(f128 (sint_to_fp (i32 (PPCmfvsr f64:$src)))), + (f128 (XSCVSDQP (VEXTSW2Ds $src)))>; + def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; def : Pat<(f128 (uint_to_fp i64:$src)), (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; + def : Pat<(f128 (uint_to_fp (i64 (PPCmfvsr f64:$src)))), + (f128 (XSCVUDQP $src))>; // Convert (Un)Signed Word -> QP. def : Pat<(f128 (sint_to_fp i32:$src)), @@ -3220,6 +3227,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (f128 (XSCVUDQP (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>; } + + // Unsiged int in vsx register -> QP + def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), + (f128 (XSCVUDQP + (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; } // IsBigEndian, HasP9Vector let Predicates = [IsLittleEndian, HasP9Vector] in { @@ -3286,6 +3298,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (EXTRACT_SUBREG (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; } + + // Unsiged int in vsx register -> QP + def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), + (f128 (XSCVUDQP + (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; } // IsLittleEndian, HasP9Vector // Convert (Un)Signed DWord in memory -> QP |
