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authorBrian Gaeke <gaeke@uiuc.edu>2003-09-16 15:38:05 +0000
committerBrian Gaeke <gaeke@uiuc.edu>2003-09-16 15:38:05 +0000
commit666b18f1a6ff098c27f11d61bf7aff75f4da6599 (patch)
tree643219e030ca49850b8510077a5e5fbfaaf87687 /llvm/lib
parentf915d9e238661e6d9a334d339edb72167051b4f1 (diff)
downloadbcm5719-llvm-666b18f1a6ff098c27f11d61bf7aff75f4da6599.tar.gz
bcm5719-llvm-666b18f1a6ff098c27f11d61bf7aff75f4da6599.zip
Fix typo in comment. Take out some random whitespace.
(Partial merge from my working file) llvm-svn: 8564
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp5
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index a04d4b8cda1..6cb241a37a9 100644
--- a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
//----------------------------------------------------------------------------
-// The entry pont to Register Allocation
+// The entry point to Register Allocation
//----------------------------------------------------------------------------
void PhyRegAlloc::allocateRegisters()
{
-
// make sure that we put all register classes into the RegClassList
// before we call constructLiveRanges (now done in the constructor of
// PhyRegAlloc class).
//
LRI.constructLiveRanges(); // create LR info
-
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI.printLiveRanges();
@@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters()
buildInterferenceGraphs(); // build IGs in all reg classes
-
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
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