Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem

encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.

llvm-svn: 113983

1 files changed, 17 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 864c5f9dbbd..4c97b82414c 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1352,6 +1352,21 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
     SrcReg = MI->getOperand(0).getReg();
     CmpValue = MI->getOperand(1).getImm();
     return true;
+  case ARM::TSTri: {
+    MachineBasicBlock::const_iterator MII(MI);
+    if (MI->getParent()->begin() == MII)
+      return false;
+    const MachineInstr *AND = llvm::prior(MII);
+    if (AND->getOpcode() != ARM::ANDri)
+      return false;
+    if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
+        MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
+      SrcReg = AND->getOperand(0).getReg();
+      CmpValue = 0;
+      return true;
+    }
+    }
+    break;
   }
 
   return false;
@@ -1401,6 +1416,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
   switch (MI->getOpcode()) {
   default: break;
   case ARM::ADDri:
+  case ARM::ANDri:
+  case ARM::t2ANDri:
   case ARM::SUBri:
   case ARM::t2ADDri:
   case ARM::t2SUBri: