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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-10-11 21:51:33 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-10-11 21:51:33 +0000 |
| commit | 66048fed828987eff8db73bdbe878b06ee941338 (patch) | |
| tree | 621310a637faf3030c2feffe4d7fc15b97815764 /llvm/lib | |
| parent | 5ebe3511b35d41b9364be62a28966e279fc568b0 (diff) | |
| download | bcm5719-llvm-66048fed828987eff8db73bdbe878b06ee941338.tar.gz bcm5719-llvm-66048fed828987eff8db73bdbe878b06ee941338.zip | |
[mips] Store 64-bit `li.d' operand as a single 8-byte value
Now assembler generates two consecutive `.4byte` directives to store
64-bit `li.d' operand. The first directive stores high 4-byte of the
value. The second directive stores low 4-byte of the value. But on
64-bit system we load this value at once and get wrong result if the
system is little-endian.
This patch fixes the bug. It stores the `li.d' operand as a single
8-byte value.
Differential Revision: https://reviews.llvm.org/D68778
llvm-svn: 374598
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 56d5e083493..24da28c89f3 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3433,8 +3433,8 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, getStreamer().SwitchSection(ReadOnlySection); getStreamer().EmitLabel(Sym, IDLoc); - getStreamer().EmitIntValue(HiImmOp64, 4); - getStreamer().EmitIntValue(LoImmOp64, 4); + getStreamer().EmitValueToAlignment(8); + getStreamer().EmitIntValue(ImmOp64, 8); getStreamer().SwitchSection(CS); if (emitPartialAddress(TOut, IDLoc, Sym)) @@ -3519,8 +3519,8 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, getStreamer().SwitchSection(ReadOnlySection); getStreamer().EmitLabel(Sym, IDLoc); - getStreamer().EmitIntValue(HiImmOp64, 4); - getStreamer().EmitIntValue(LoImmOp64, 4); + getStreamer().EmitValueToAlignment(8); + getStreamer().EmitIntValue(ImmOp64, 8); getStreamer().SwitchSection(CS); if (emitPartialAddress(TOut, IDLoc, Sym)) |
