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author | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-08-01 09:03:23 +0000 |
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committer | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-08-01 09:03:23 +0000 |
commit | 64c10ba8e23dcf77c97def98c4a16eefa2b21d8d (patch) | |
tree | 25bda35f753c6dff98e64a50cada4e762d03ac69 /llvm/lib | |
parent | 676dc17db09090782ad17fadabc765264f1ca435 (diff) | |
download | bcm5719-llvm-64c10ba8e23dcf77c97def98c4a16eefa2b21d8d.tar.gz bcm5719-llvm-64c10ba8e23dcf77c97def98c4a16eefa2b21d8d.zip |
[MIPS GlobalISel] Select global address
Select G_GLOBAL_VALUE for position dependent code.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D49803
llvm-svn: 338499
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 27 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 3 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 |
3 files changed, 31 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index af0ac006bc9..6c5b83021f7 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -166,6 +166,33 @@ bool MipsInstructionSelector::select(MachineInstr &I, I.eraseFromParent(); return true; } + case G_GLOBAL_VALUE: { + if (MF.getTarget().isPositionIndependent()) + return false; + + const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); + unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LUi, *ADDiu; + + LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) + .addDef(LUiReg) + .addGlobalAddress(GVal); + LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); + + ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) + .addDef(I.getOperand(0).getReg()) + .addUse(LUiReg) + .addGlobalAddress(GVal); + ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); + + if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) + return false; + if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } default: return false; diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index da6f9dabdaa..fb259516be0 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -36,6 +36,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { getActionDefinitionsBuilder(G_FRAME_INDEX) .legalFor({p0}); + getActionDefinitionsBuilder(G_GLOBAL_VALUE) + .legalFor({p0}); + computeTables(); verify(*ST.getInstrInfo()); } diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index cef21f44720..35113507921 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -88,6 +88,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { break; case G_CONSTANT: case G_FRAME_INDEX: + case G_GLOBAL_VALUE: OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); break; |