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| author | Craig Topper <craig.topper@gmail.com> | 2016-04-24 06:27:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-04-24 06:27:35 +0000 |
| commit | 6469a39f51b1b2c516488bda59756f88d1750612 (patch) | |
| tree | 2828e4421a0c80bf67450fb3342c8f98bc568dc0 /llvm/lib | |
| parent | ca2c54e04e7e2a7e59058d56c2f2bd6c2758c171 (diff) | |
| download | bcm5719-llvm-6469a39f51b1b2c516488bda59756f88d1750612.tar.gz bcm5719-llvm-6469a39f51b1b2c516488bda59756f88d1750612.zip | |
[X86] Node need to check if AVX512 is supported when lowering vector CTLZ. The CTLZ operation is only Custom for vectors if AVX512 is enabled so if a vector gets here AVX512 is implied. NFC
llvm-svn: 267330
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e2cb59a8338..eb65a804d9f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18711,14 +18711,13 @@ static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta); } -static SDValue LowerCTLZ(SDValue Op, const X86Subtarget &Subtarget, - SelectionDAG &DAG) { +static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); MVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); SDLoc dl(Op); - if (VT.isVector() && Subtarget.hasAVX512()) + if (VT.isVector()) return LowerVectorCTLZ_AVX512(Op, DAG); Op = Op.getOperand(0); @@ -18750,8 +18749,7 @@ static SDValue LowerCTLZ(SDValue Op, const X86Subtarget &Subtarget, return Op; } -static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget &Subtarget, - SelectionDAG &DAG) { +static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); EVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); @@ -21272,8 +21270,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); - case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG); - case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG); + case ISD::CTLZ: return LowerCTLZ(Op, DAG); + case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); case ISD::CTTZ: case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG); case ISD::MUL: return LowerMUL(Op, Subtarget, DAG); |
