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| author | Jiangning Liu <jiangning.liu@arm.com> | 2014-01-26 03:27:40 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2014-01-26 03:27:40 +0000 |
| commit | 6398d839c6b36c07314ef6ae13ee332ef399f700 (patch) | |
| tree | 4253f8acb6a3f7416ed7e5fcae39612c7d6e5d62 /llvm/lib | |
| parent | cdee0edf2ab80184cd1a0e3d52fe3291db29f77a (diff) | |
| download | bcm5719-llvm-6398d839c6b36c07314ef6ae13ee332ef399f700.tar.gz bcm5719-llvm-6398d839c6b36c07314ef6ae13ee332ef399f700.zip | |
Implement pattern match from v1xx to v1xx for AArch64 Neon.
llvm-svn: 200113
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrNEON.td | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrNEON.td b/llvm/lib/Target/AArch64/AArch64InstrNEON.td index badd9e0f402..1180485b727 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrNEON.td +++ b/llvm/lib/Target/AArch64/AArch64InstrNEON.td @@ -6211,6 +6211,91 @@ defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>; defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>; defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>; +// The following is for sext/zext from v1xx to v1xx +multiclass NeonI_ext<string prefix, SDNode ExtOp> { + // v1i32 -> v1i64 + def : Pat<(v1i64 (ExtOp (v1i32 FPR32:$Rn))), + (EXTRACT_SUBREG + (v2i64 (!cast<Instruction>(prefix # "_2S") + (v2i32 (SUBREG_TO_REG (i64 0), $Rn, sub_32)), 0)), + sub_64)>; + + // v1i16 -> v1i32 + def : Pat<(v1i32 (ExtOp (v1i16 FPR16:$Rn))), + (EXTRACT_SUBREG + (v4i32 (!cast<Instruction>(prefix # "_4H") + (v4i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)), 0)), + sub_32)>; + + // v1i8 -> v1i16 + def : Pat<(v1i16 (ExtOp (v1i8 FPR8:$Rn))), + (EXTRACT_SUBREG + (v8i16 (!cast<Instruction>(prefix # "_8B") + (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), + sub_16)>; + + // v1i8 -> v1i32 + def : Pat<(v1i32 (ExtOp (v1i8 FPR8:$Rn))), + (EXTRACT_SUBREG + (v4i32 (!cast<Instruction>(prefix # "_4H") + (v4i16 (SUBREG_TO_REG (i64 0), + (v1i16 (EXTRACT_SUBREG + (v8i16 (!cast<Instruction>(prefix # "_8B") + (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), + sub_16)), + sub_16)), 0)), + sub_32)>; +} + +defm NeonI_zext : NeonI_ext<"USHLLvvi", zext>; +defm NeonI_sext : NeonI_ext<"SSHLLvvi", sext>; + +// zext v1i8 -> v1i64 +def : Pat<(v1i64 (zext (v1i8 FPR8:$Rn))), + (v1i64 (SUBREG_TO_REG (i64 0), + (v1i8 (DUPbv_B + (v16i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), + 0)), + sub_8))>; + +// zext v1i16 -> v1i64 +def : Pat<(v1i64 (zext (v1i16 FPR16:$Rn))), + (v1i64 (SUBREG_TO_REG (i64 0), + (v1i16 (DUPhv_H + (v8i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)), + 0)), + sub_16))>; + +// sext v1i8 -> v1i64 +def : Pat<(v1i64 (sext (v1i8 FPR8:$Rn))), + (EXTRACT_SUBREG + (v2i64 (SSHLLvvi_2S + (v2i32 (SUBREG_TO_REG (i64 0), + (v1i32 (EXTRACT_SUBREG + (v4i32 (SSHLLvvi_4H + (v4i16 (SUBREG_TO_REG (i64 0), + (v1i16 (EXTRACT_SUBREG + (v8i16 (SSHLLvvi_8B + (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), + sub_16)), + sub_16)), 0)), + sub_32)), + sub_32)), 0)), + sub_64)>; + + +// sext v1i16 -> v1i64 +def : Pat<(v1i64 (sext (v1i16 FPR16:$Rn))), + (EXTRACT_SUBREG + (v2i64 (SSHLLvvi_2S + (v2i32 (SUBREG_TO_REG (i64 0), + (v1i32 (EXTRACT_SUBREG + (v4i32 (SSHLLvvi_4H + (v4i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)), 0)), + sub_32)), + sub_32)), 0)), + sub_64)>; + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// |
