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| author | Jim Laskey <jlaskey@mac.com> | 2005-09-27 17:32:45 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-09-27 17:32:45 +0000 |
| commit | 63523f98d5227d8c98099cf60f6ee4dfa728a2ca (patch) | |
| tree | dcb63c13f377ae13ce10efda374daa8f478a0ec1 /llvm/lib | |
| parent | 57432e717e778f9878ce0fdf4e8ba4504d8f3752 (diff) | |
| download | bcm5719-llvm-63523f98d5227d8c98099cf60f6ee4dfa728a2ca.tar.gz bcm5719-llvm-63523f98d5227d8c98099cf60f6ee4dfa728a2ca.zip | |
Remove some redundancies.
llvm-svn: 23469
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 164529884d5..c4e72072103 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -197,7 +197,6 @@ struct ScheduleInfo { SDOperand Op; // Operand information unsigned Latency; // Cycles to complete instruction unsigned ResourceSet; // Bit vector of usable resources - bool IsBoundary; // Do not shift passed this instruction. unsigned Slot; // Operand's time slot // Ctor. @@ -205,7 +204,6 @@ struct ScheduleInfo { : Op(op) , Latency(0) , ResourceSet(0) - , IsBoundary(false) , Slot(0) {} }; @@ -452,10 +450,10 @@ void SimpleSched::GatherOperandInfo() { MachineOpCode TOpc = Op.getTargetOpcode(); // FIXME SI->Latency = std::max(1, TII.maxLatency(TOpc)); // FIXME SI->ResourceSet = TII.resources(TOpc); - // There is a cost for keeping values across a call. - SI->IsBoundary = TII.isCall(TOpc); - - if (TII.isLoad(TOpc)) { + if (TII.isCall(TOpc)) { + SI->ResourceSet = RSInteger; + SI->Latency = 40; + } else if (TII.isLoad(TOpc)) { SI->ResourceSet = RSLoadStore; SI->Latency = 5; } else if (TII.isStore(TOpc)) { @@ -526,7 +524,11 @@ bool SimpleSched::isStrongDependency(SDNode *A, SDNode *B) { /// conflict with operands of B. bool SimpleSched::isWeakDependency(SDNode *A, SDNode *B) { // TODO check for conflicting real registers and aliases +#if 0 // Since we are in SSA form and not checking register aliasing return A->getOpcode() == ISD::EntryToken || isStrongDependency(B, A); +#else + return A->getOpcode() == ISD::EntryToken; +#endif } /// ScheduleBackward - Schedule instructions so that any long latency @@ -554,8 +556,7 @@ void SimpleSched::ScheduleBackward() { if (isStrongDependency(SI->Op, Other->Op)) { Slot = Other->Slot + Other->Latency; break; - } else if (SI->IsBoundary || Other->IsBoundary || - isWeakDependency(SI->Op, Other->Op)) { + } else if (isWeakDependency(SI->Op, Other->Op)) { Slot = Other->Slot; break; } @@ -609,8 +610,7 @@ void SimpleSched::ScheduleForward() { if (isStrongDependency(Other->Op, SI->Op)) { Slot = Other->Slot + Other->Latency; break; - } else if (SI->IsBoundary || Other->IsBoundary || - isWeakDependency(Other->Op, SI->Op)) { + } else if (isWeakDependency(Other->Op, SI->Op)) { Slot = Other->Slot; break; } |

