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| author | Igor Breger <igor.breger@intel.com> | 2016-06-07 13:08:45 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-06-07 13:08:45 +0000 |
| commit | 61e628591f21c6d6e8ae11f1debf9c67fdadc48a (patch) | |
| tree | 74e54872ccd60fdb71d144bace7916648ab66a0d /llvm/lib | |
| parent | 6b0634b3040a2dc37f4d41fceec1c415d9981deb (diff) | |
| download | bcm5719-llvm-61e628591f21c6d6e8ae11f1debf9c67fdadc48a.tar.gz bcm5719-llvm-61e628591f21c6d6e8ae11f1debf9c67fdadc48a.zip | |
[AVX512] Fix load opcode for fast isel.
Differential Revision: http://reviews.llvm.org/D21067
llvm-svn: 272006
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index d06d7e22d49..d62a3c7a78b 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -452,7 +452,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, assert(Subtarget->hasAVX512()); // Note: There are a lot more choices based on type with AVX-512, but // there's really no advantage when the load isn't masked. - Opc = (Alignment >= 64) ? X86::VMOVDQA64Zmr : X86::VMOVDQU64Zmr; + Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; RC = &X86::VR512RegClass; break; } |
