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| author | Craig Topper <craig.topper@intel.com> | 2018-07-15 06:03:19 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-07-15 06:03:19 +0000 |
| commit | 60ce856134e1f667744ced33d2c61a58b6be285b (patch) | |
| tree | 944864eaf7ccf32d8dff4f1907a2c107115879f6 /llvm/lib | |
| parent | e32792d8bdd20fc122988c92e70c2b0aec4242dc (diff) | |
| download | bcm5719-llvm-60ce856134e1f667744ced33d2c61a58b6be285b.tar.gz bcm5719-llvm-60ce856134e1f667744ced33d2c61a58b6be285b.zip | |
[X86] Add some optsize patterns for 256-bit X86vzmovl.
These patterns use VMOVSS/SD. Without optsize we use BLENDI instead.
llvm-svn: 337119
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 5c8b612f49b..eb6a3323491 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -304,6 +304,25 @@ let Predicates = [UseAVX, OptForSize] in { (VMOVSSrr (v4f32 (V_SET0)), VR128:$src)>; def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), (VMOVSSrr (v4i32 (V_SET0)), VR128:$src)>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSSrr (v4f32 (V_SET0)), + (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSSrr (v4i32 (V_SET0)), + (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSDrr (v2f64 (V_SET0)), + (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSDrr (v2i64 (V_SET0)), + (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>; } let Predicates = [UseSSE1] in { |
