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author | Chen Zheng <czhengsz@cn.ibm.com> | 2018-12-28 01:02:35 +0000 |
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committer | Chen Zheng <czhengsz@cn.ibm.com> | 2018-12-28 01:02:35 +0000 |
commit | 5ede950df9e99dc813f9251173cc6d38bf6293e8 (patch) | |
tree | 3c3bc7df670f1a9195bb16c42323cd443677bd1c /llvm/lib | |
parent | 10828c39cbb30f376674a5c253330988dffd0399 (diff) | |
download | bcm5719-llvm-5ede950df9e99dc813f9251173cc6d38bf6293e8.tar.gz bcm5719-llvm-5ede950df9e99dc813f9251173cc6d38bf6293e8.zip |
[PowerPC] fix register class after converting X-FORM instruction to D-FORM instruction
Differential Revision: https://reviews.llvm.org/D55806
llvm-svn: 350111
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index d26af451303..1b9d5d2d8e0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3438,15 +3438,20 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, if (III.OpNoForForwarding != III.ImmOpNo) swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo); - // If the R0/X0 register is special for the original instruction and not for - // the new instruction (or vice versa), we need to fix up the register class. + // If the special R0/X0 register index are different for original instruction + // and new instruction, we need to fix up the register class in new + // instruction. if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) { - if (!III.ZeroIsSpecialOrig) { + if (III.ZeroIsSpecialNew) { + // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no + // need to fix up register class. unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg(); - const TargetRegisterClass *NewRC = - MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? - &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; - MRI.setRegClass(RegToModify, NewRC); + if (TargetRegisterInfo::isVirtualRegister(RegToModify)) { + const TargetRegisterClass *NewRC = + MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? + &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; + MRI.setRegClass(RegToModify, NewRC); + } } } return true; |