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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:47 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:47 +0000 |
| commit | 5e208dc21bbf926bcb9e00a8fdbe71cc6d139986 (patch) | |
| tree | 9c3d1b6eccea73caabb77e25fcc0e4e05eb04f27 /llvm/lib | |
| parent | a248becd6cffe048a29cc02062bd0cc0d6e331ca (diff) | |
| download | bcm5719-llvm-5e208dc21bbf926bcb9e00a8fdbe71cc6d139986.tar.gz bcm5719-llvm-5e208dc21bbf926bcb9e00a8fdbe71cc6d139986.zip | |
Fix itins for VPAL
llvm-svn: 100658
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index d313754afb9..03b0ce891fb 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -516,11 +516,11 @@ def CortexA8Itineraries : ProcessorItineraries<[ // // Double-register Integer Pair Add Long InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 1]>, // // Quad-register Integer Pair Add Long InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 1]>, // // Double-register Absolute Difference and Accumulate InstrItinData<IIC_VABAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, @@ -923,7 +923,21 @@ def CortexA9Itineraries : ProcessorItineraries<[ // Extra 3 latency cycle since wbck is 6 cycles InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]> + InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>, + // + // Double-register Integer Pair Add Long + InstrItinData<IIC_VPALiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 1]>, + // + // Quad-register Integer Pair Add Long + InstrItinData<IIC_VPALiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [6, 3, 1]> ]>; |
