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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-07-15 19:39:31 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-07-15 19:39:31 +0000
commit5dfd4660329054f492583939ba69335a352b89dc (patch)
tree6eca06117887f796d03b4ded3136c28679dad57c /llvm/lib
parent434d664095b2417453c9e86943c9a94ae1d4bd47 (diff)
downloadbcm5719-llvm-5dfd4660329054f492583939ba69335a352b89dc.tar.gz
bcm5719-llvm-5dfd4660329054f492583939ba69335a352b89dc.zip
AMDGPU/GlobalISel: Fix G_ICMP for wave32
llvm-svn: 366114
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 317a9b5c08c..5a73b0d1139 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -583,7 +583,7 @@ bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
- DebugLoc DL = I.getDebugLoc();
+ const DebugLoc &DL = I.getDebugLoc();
unsigned SrcReg = I.getOperand(2).getReg();
unsigned Size = RBI.getSizeInBits(SrcReg, MRI, TRI);
@@ -616,7 +616,7 @@ bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const {
.add(I.getOperand(2))
.add(I.getOperand(3));
RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
- AMDGPU::SReg_64RegClass, MRI);
+ *TRI.getBoolRC(), MRI);
bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
I.eraseFromParent();
return Ret;
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