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author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-10 04:38:31 +0000 |
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committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-10 04:38:31 +0000 |
commit | 5bfefb6a8f07f9ea73277043ff6c824851c00a10 (patch) | |
tree | 5ab32278f1b45fa9709448f6f9e574481518235b /llvm/lib | |
parent | c38786be00778e8ad87fb0d50c3ce00a7ca84efb (diff) | |
download | bcm5719-llvm-5bfefb6a8f07f9ea73277043ff6c824851c00a10.tar.gz bcm5719-llvm-5bfefb6a8f07f9ea73277043ff6c824851c00a10.zip |
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:
ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.
Thanks to Joerg Sonnenberger for the tests!
llvm-svn: 198914
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 72 |
1 files changed, 45 insertions, 27 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index cbf67c96458..b80eefd398c 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -2444,23 +2444,28 @@ def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins addr_offset_none:$addr, am2offset_imm:$offset), - IndexModePost, LdFrm, IIC_iLoad_ru, - "ldrt", "\t$Rt, $addr, $offset", - "$addr.base = $Rn_wb", []> { +class LDRTImmediate<bit has_offset, string args, dag iops> + : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops, + IndexModePost, LdFrm, IIC_iLoad_ru, + "ldrt", args, "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; - let Inst{23} = offset{12}; + let Inst{23} = !if(has_offset, offset{12}, 1); let Inst{21} = 1; // overwrite let Inst{19-16} = addr; - let Inst{11-0} = offset{11-0}; + let Inst{11-0} = !if(has_offset, offset{11-0}, 0); let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } +def LDRT_POST_IMM + : LDRTImmediate<1, "\t$Rt, $addr, $offset", + (ins addr_offset_none:$addr, am2offset_imm:$offset)>; +def LDRT_POST_IMM_0 + : LDRTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>; + def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, LdFrm, IIC_iLoad_bh_ru, @@ -2480,23 +2485,28 @@ def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins addr_offset_none:$addr, am2offset_imm:$offset), +class LDRBTImmediate<bit has_offset, string args, dag iops> + : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops, IndexModePost, LdFrm, IIC_iLoad_bh_ru, - "ldrbt", "\t$Rt, $addr, $offset", - "$addr.base = $Rn_wb", []> { + "ldrbt", args, "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; - let Inst{23} = offset{12}; + let Inst{23} = !if(has_offset, offset{12}, 1); let Inst{21} = 1; // overwrite let Inst{19-16} = addr; - let Inst{11-0} = offset{11-0}; + let Inst{11-0} = !if(has_offset, offset{11-0}, 0); let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } +def LDRBT_POST_IMM + : LDRBTImmediate<1, "\t$Rt, $addr, $offset", + (ins addr_offset_none:$addr, am2offset_imm:$offset)>; +def LDRBT_POST_IMM_0 + : LDRBTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>; + multiclass AI3ldrT<bits<4> op, string opc> { def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), (ins addr_offset_none:$addr, postidx_imm8:$offset), @@ -2748,23 +2758,27 @@ def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), - IndexModePost, StFrm, IIC_iStore_bh_ru, - "strbt", "\t$Rt, $addr, $offset", - "$addr.base = $Rn_wb", []> { +class STRBTImmediate<bit has_offset, string args, dag iops> + : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm, + IIC_iStore_bh_ru, "strbt", args, "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; - let Inst{23} = offset{12}; + let Inst{23} = !if(has_offset, offset{12}, 1); let Inst{21} = 1; // overwrite let Inst{19-16} = addr; - let Inst{11-0} = offset{11-0}; + let Inst{11-0} = !if(has_offset, offset{11-0}, 0); let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } +def STRBT_POST_IMM + : STRBTImmediate<1, "\t$Rt, $addr, $offset", + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>; +def STRBT_POST_IMM_0 + : STRBTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>; + let mayStore = 1, neverHasSideEffects = 1 in { def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), @@ -2785,22 +2799,26 @@ def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), - IndexModePost, StFrm, IIC_iStore_ru, - "strt", "\t$Rt, $addr, $offset", - "$addr.base = $Rn_wb", []> { +class STRTImmediate<bit has_offset, string args, dag iops> + : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm, + IIC_iStore_ru, "strt", args, "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; - let Inst{23} = offset{12}; + let Inst{23} = !if(has_offset, offset{12}, 1); let Inst{21} = 1; // overwrite let Inst{19-16} = addr; - let Inst{11-0} = offset{11-0}; + let Inst{11-0} = !if(has_offset, offset{11-0}, 0); let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } + +def STRT_POST_IMM + : STRTImmediate<1, "\t$Rt, $addr, $offset", + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>; +def STRT_POST_IMM_0 + : STRTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>; } |