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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 16:42:50 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 16:42:50 +0000 |
| commit | 5af82a7ae1eea8477be87bb9003aee5583003562 (patch) | |
| tree | 35a151e01e6de2b380de7398c6d154e94e96dcd9 /llvm/lib | |
| parent | 1db6486fb1648b978ab048c47f120f9f274f92f3 (diff) | |
| download | bcm5719-llvm-5af82a7ae1eea8477be87bb9003aee5583003562.tar.gz bcm5719-llvm-5af82a7ae1eea8477be87bb9003aee5583003562.zip | |
AMDGPU: Fix not including v2i16/v2f16 in register class
llvm-svn: 298390
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 86050ea23df..fc808011cd8 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -271,7 +271,7 @@ def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f1 let AllocationPriority = 7; } -def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32, +def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { let AllocationPriority = 7; } |
