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authorChris Lattner <sabre@nondot.org>2006-04-05 00:03:57 +0000
committerChris Lattner <sabre@nondot.org>2006-04-05 00:03:57 +0000
commit5a528e565b6e5e331dbb3fdbb084ac8f5d384f34 (patch)
treebd34bf0bdb607d58de1e27cb444e8dd3ea199ea6 /llvm/lib
parent7ef2376d8e236d673792d6fa871771fce0003756 (diff)
downloadbcm5719-llvm-5a528e565b6e5e331dbb3fdbb084ac8f5d384f34.tar.gz
bcm5719-llvm-5a528e565b6e5e331dbb3fdbb084ac8f5d384f34.zip
Add m[tf]vscr instructions.
llvm-svn: 27421
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrAltivec.td7
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFormats.td27
2 files changed, 34 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 526523f0ccc..0569e47b2f0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -93,6 +93,13 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
[(set VRRC:$rD, (v4f32 (undef)))]>;
+def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
+ "mfvcr $vD", LdStGeneral,
+ [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
+def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
+ "mtvcr $vB", LdStGeneral,
+ [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
+
let isLoad = 1, PPC970_Unit = 2 in { // Loads.
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 805e1258c53..c3a78e65bf9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -697,6 +697,33 @@ class VXForm_3<bits<11> xo, dag OL, string asmstr,
let Inst{21-31} = xo;
}
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = 0;
+ let Inst{16-20} = 0;
+ let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = 0;
+ let Inst{11-15} = 0;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
// E-4 VXR-Form
class VXRForm_1<bits<10> xo, dag OL, string asmstr,
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