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| author | David Greene <greened@obbligato.org> | 2019-05-28 15:37:01 +0000 |
|---|---|---|
| committer | David Greene <greened@obbligato.org> | 2019-05-28 15:37:01 +0000 |
| commit | 561fcc0d63caca46e46a746db482a1c6895b2ac4 (patch) | |
| tree | 03e64e5f43c058f13f56c24e964e43d39e29984e /llvm/lib | |
| parent | ebe22a1774ed433534a63af0bf5fdc5b5bd821b4 (diff) | |
| download | bcm5719-llvm-561fcc0d63caca46e46a746db482a1c6895b2ac4.tar.gz bcm5719-llvm-561fcc0d63caca46e46a746db482a1c6895b2ac4.zip | |
[X86-64] Fix 256-bit SET0 lowering for non-VLX targets
If we don't have VLX then 256-bit SET0 should be lowered
to VPXOR with ZMM registers. This restores functionality
accidentally removed by r309926.
Differential Revision: https://reviews.llvm.org/D62415
llvm-svn: 361843
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 4ec80d90d9a..20d3cf0d927 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3932,6 +3932,12 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MIB.addReg(SrcReg, RegState::ImplicitDefine); return true; } + if (MI.getOpcode() == X86::AVX512_256_SET0) { + // No VLX so we must reference a zmm. + unsigned ZReg = + TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); + MIB->getOperand(0).setReg(ZReg); + } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } case X86::V_SETALLONES: |
