[mips] Fix floating point branch, comparison, and conditional move instructions

to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233

2 files changed, 4 insertions, 4 deletions

diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td
index cb0112afb74..8f5c4dcb445 100644
--- a/llvm/lib/Target/Mips/MipsCondMov.td
+++ b/llvm/lib/Target/Mips/MipsCondMov.td
@@ -37,7 +37,7 @@ class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
   InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
          !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
          [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
-  let Uses = [FCR31];
+  let Uses = [FCC0];
   let Constraints = "$F = $rd";
 }
 
@@ -47,7 +47,7 @@ class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
   InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
          !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
          [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
-  let Uses = [FCR31];
+  let Uses = [FCC0];
   let Constraints = "$F = $fd";
 }
 
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index fc7ea301816..6fe469acc70 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -194,7 +194,7 @@ class BC1F_FT<string opstr, InstrItinClass Itin,
   let isTerminator = 1;
   let hasDelaySlot = 1;
   let Defs = [AT];
-  let Uses = [FCR31];
+  let Uses = [FCC0];
 }
 
 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
@@ -202,7 +202,7 @@ class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
   InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
          !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
          [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
-  let Defs = [FCR31];
+  let Defs = [FCC0];
   let isCodeGenOnly = 1;
 }