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| author | Craig Topper <craig.topper@intel.com> | 2018-06-13 00:04:08 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-13 00:04:08 +0000 |
| commit | 55488731be1b6df0a92683996ff2e34a06bae90b (patch) | |
| tree | faf822de2cd241a68accbceca75efcc2909c6667 /llvm/lib | |
| parent | 4f9cac667ba4a50a6e8c46a3c5337751beaa3430 (diff) | |
| download | bcm5719-llvm-55488731be1b6df0a92683996ff2e34a06bae90b.tar.gz bcm5719-llvm-55488731be1b6df0a92683996ff2e34a06bae90b.zip | |
[X86] Mark all instructions that have masked store semantics with NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator.
Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore.
llvm-svn: 334563
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 6d3b56f88e4..59457f9dc78 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -835,7 +835,7 @@ multiclass vextract_for_size_split<int Opcode, "vextract" # To.EltTypeName # "x" # To.NumElts # "\t{$idx, $src1, $dst {${mask}}|" "$dst {${mask}}, $src1, $idx}", []>, - EVEX_K, EVEX, Sched<[SchedMR]>; + EVEX_K, EVEX, Sched<[SchedMR]>, NotMemoryFoldable; } } @@ -3385,7 +3385,8 @@ multiclass avx512_store<bits<8> opc, string OpcodeStr, string BaseName, def mrk : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src), OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}", - [], _.ExeDomain>, EVEX, EVEX_K, Sched<[Sched.MR]>; + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[Sched.MR]>, + NotMemoryFoldable; def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)), (!cast<Instruction>(BaseName#_.ZSuffix##mrk) addr:$ptr, @@ -3889,7 +3890,8 @@ multiclass avx512_move_scalar<string asm, SDNode OpNode, def mrk: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src), !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), - [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFStore]>; + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFStore]>, + NotMemoryFoldable; } defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>, @@ -8052,7 +8054,7 @@ multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src, def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", []>, - EVEX_K, Sched<[MR]>; + EVEX_K, Sched<[MR]>, NotMemoryFoldable; } } @@ -8644,8 +8646,8 @@ multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode, def mrk : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src), OpcodeStr # "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}", []>, - EVEX, EVEX_K, Sched<[sched.Folded]>; - }//mayStore = 1, mayLoad = 1, hasSideEffects = 0 + EVEX, EVEX_K, Sched<[sched.Folded]>, NotMemoryFoldable; + }//mayStore = 1, hasSideEffects = 0 } multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo, |

