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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-09 12:32:56 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-09 12:32:56 +0000 |
| commit | 54077dcfcb4567c83d704dde2c8d106e9f7dead0 (patch) | |
| tree | 5b48ec1a41a2197047e850bdace28810875b6954 /llvm/lib | |
| parent | 88347796440212e7acd97b4e675c568ce5cf1d53 (diff) | |
| download | bcm5719-llvm-54077dcfcb4567c83d704dde2c8d106e9f7dead0.tar.gz bcm5719-llvm-54077dcfcb4567c83d704dde2c8d106e9f7dead0.zip | |
[AArch64][SVE] Asm: Support for TBL instruction.
Support for SVE's TBL instruction for programmable table
lookup/permute using vector of element indices, e.g.
tbl z0.d, { z1.d }, z2.d
stores elements from z1, indexed by elements from z2, into z0.
llvm-svn: 336544
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 33 |
2 files changed, 35 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index e10c527140f..686bd0a28f6 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -539,6 +539,8 @@ let Predicates = [HasSVE] in { defm ADR_LSL_ZZZ_S : sve_int_bin_cons_misc_0_a_32_lsl<0b10, "adr">; defm ADR_LSL_ZZZ_D : sve_int_bin_cons_misc_0_a_64_lsl<0b11, "adr">; + defm TBL_ZZZ : sve_int_perm_tbl<"tbl">; + defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 8ac45052c5b..6fd617f3087 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -571,6 +571,39 @@ multiclass sve_int_perm_dup_i<string asm> { (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; } +class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty, + RegisterOperand VecList> +: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_perm_tbl<string asm> { + def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>; + def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>; + def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>; + def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>; + + def : InstAlias<asm # "\t$Zd, $Zn, $Zm", + (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; + def : InstAlias<asm # "\t$Zd, $Zn, $Zm", + (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>; + def : InstAlias<asm # "\t$Zd, $Zn, $Zm", + (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>; + def : InstAlias<asm # "\t$Zd, $Zn, $Zm", + (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; +} //===----------------------------------------------------------------------===// // SVE Vector Select Group |
