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author | Jim Laskey <jlaskey@mac.com> | 2005-10-26 17:28:23 +0000 |
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committer | Jim Laskey <jlaskey@mac.com> | 2005-10-26 17:28:23 +0000 |
commit | 53ad110490853fd5cb40429dcad3924068278b54 (patch) | |
tree | 97d62bafdf84791badf6abc6fbf24424f93bd8c4 /llvm/lib | |
parent | 38a1b00a0fd36d948c3aef2a5c6d42bbb74de305 (diff) | |
download | bcm5719-llvm-53ad110490853fd5cb40429dcad3924068278b54.tar.gz bcm5719-llvm-53ad110490853fd5cb40429dcad3924068278b54.zip |
Add attribute name and type to SubtargetFeatures.
llvm-svn: 24012
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Alpha/Alpha.td | 6 | ||||
-rw-r--r-- | llvm/lib/Target/PowerPC/PPC.td | 10 | ||||
-rw-r--r-- | llvm/lib/Target/Target.td | 10 |
3 files changed, 18 insertions, 8 deletions
diff --git a/llvm/lib/Target/Alpha/Alpha.td b/llvm/lib/Target/Alpha/Alpha.td index ae2286c06be..7cbb0f181f7 100644 --- a/llvm/lib/Target/Alpha/Alpha.td +++ b/llvm/lib/Target/Alpha/Alpha.td @@ -20,8 +20,10 @@ include "../Target.td" // Subtarget Features //===----------------------------------------------------------------------===// -def FeatureCIX : SubtargetFeature<"CIX", "Enable CIX extentions">; -def FeatureFIX : SubtargetFeature<"FIX", "Enable FIX extentions">; +def FeatureCIX : SubtargetFeature<"CIX", "bool", "HasCT", + "Enable CIX extentions">; +def FeatureFIX : SubtargetFeature<"FIX", "bool", "HasF2I", + "Enable FIX extentions">; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 93edd0dc348..1de838f7aaa 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -19,15 +19,15 @@ include "../Target.td" // PowerPC Subtarget features. // -def Feature64Bit : SubtargetFeature<"64bit", +def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit", "Enable 64-bit instructions">; -def Feature64BitRegs : SubtargetFeature<"64bitregs", +def Feature64BitRegs : SubtargetFeature<"64bitregs", "bool", "Has64BitRegs", "Enable 64-bit registers [beta]">; -def FeatureAltivec : SubtargetFeature<"altivec", +def FeatureAltivec : SubtargetFeature<"altivec", "bool", "HasAltivec", "Enable Altivec instructions">; -def FeatureGPUL : SubtargetFeature<"gpul", +def FeatureGPUL : SubtargetFeature<"gpul", "bool", "IsGigaProcessor", "Enable GPUL instructions">; -def FeatureFSqrt : SubtargetFeature<"fsqrt", +def FeatureFSqrt : SubtargetFeature<"fsqrt", "bool", "HasFSQRT", "Enable the fsqrt instruction">; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td index 3ce329f9f76..7de2d3f5eb4 100644 --- a/llvm/lib/Target/Target.td +++ b/llvm/lib/Target/Target.td @@ -252,12 +252,20 @@ class Target { //===----------------------------------------------------------------------===// // SubtargetFeature - A characteristic of the chip set. // -class SubtargetFeature<string n, string d> { +class SubtargetFeature<string n, string t, string a, string d> { // Name - Feature name. Used by command line (-mattr=) to determine the // appropriate target chip. // string Name = n; + // Type - Type of attribute to be set by feature. + // + string Type = t; + + // Attribute - Attribute to be set by feature. + // + string Attribute = a; + // Desc - Feature description. Used by command line (-mattr=) to display help // information. // |