diff options
author | Evan Cheng <evan.cheng@apple.com> | 2008-09-10 20:08:45 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2008-09-10 20:08:45 +0000 |
commit | 534fe1c4050808075f14b79879f15c12ee895150 (patch) | |
tree | 2ce21bb04df7a9b8afcedf541cf7fcb78134148c /llvm/lib | |
parent | 2752a17a00f13d4c6a882f774ca4946fa2bdc03b (diff) | |
download | bcm5719-llvm-534fe1c4050808075f14b79879f15c12ee895150.tar.gz bcm5719-llvm-534fe1c4050808075f14b79879f15c12ee895150.zip |
Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands.
llvm-svn: 56065
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/VirtRegMap.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 4fd0ad44b05..e783e04a616 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -832,8 +832,10 @@ namespace { } Spills.ClobberPhysReg(NewPhysReg); Spills.ClobberPhysReg(NewOp.PhysRegReused); - - MI->getOperand(NewOp.Operand).setReg(NewPhysReg); + + unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg(); + unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; + MI->getOperand(NewOp.Operand).setReg(RReg); Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); --MII; |