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author | Davide Italiano <davide@freebsd.org> | 2016-10-31 22:56:56 +0000 |
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committer | Davide Italiano <davide@freebsd.org> | 2016-10-31 22:56:56 +0000 |
commit | 51cbe13a3ff507a14ab8d27a0505c30b33af7073 (patch) | |
tree | d8cb98e672fa5fa1e48057e4a1ec7d12960a1bf1 /llvm/lib | |
parent | 2792dccb36db377e0669dedcbca37ef53bde9669 (diff) | |
download | bcm5719-llvm-51cbe13a3ff507a14ab8d27a0505c30b33af7073.tar.gz bcm5719-llvm-51cbe13a3ff507a14ab8d27a0505c30b33af7073.zip |
[Hexagon] Garbage collect dead code.
llvm-svn: 285654
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index baa3b8bdc13..2760e16bd0f 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -195,7 +195,6 @@ namespace { unsigned DstSR, const MachineOperand &PredOp, bool PredSense, bool ReadUndef, bool ImpUse); bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs); - bool splitInBlock(MachineBasicBlock &B, std::set<unsigned> &UpdRegs); bool isPredicable(MachineInstr *MI); MachineInstr *getReachingDefForPred(RegisterRef RD, @@ -651,22 +650,6 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, return true; } - -/// Split all MUX instructions in the given block into pairs of conditional -/// transfers. -bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B, - std::set<unsigned> &UpdRegs) { - bool Changed = false; - MachineBasicBlock::iterator I, E, NextI; - for (I = B.begin(), E = B.end(); I != E; I = NextI) { - NextI = std::next(I); - if (isCondset(*I)) - Changed |= split(*I, UpdRegs); - } - return Changed; -} - - bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) return false; |