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authorChris Lattner <sabre@nondot.org>2001-09-19 13:47:12 +0000
committerChris Lattner <sabre@nondot.org>2001-09-19 13:47:12 +0000
commit518da4f3cd782d4f6fd98013b5bf69bf63cc7944 (patch)
tree22253c078c2be69e07ec0e1c81e0b1b6341fb3a6 /llvm/lib
parent219f777badda38c57359749560aa079f636db34c (diff)
downloadbcm5719-llvm-518da4f3cd782d4f6fd98013b5bf69bf63cc7944.tar.gz
bcm5719-llvm-518da4f3cd782d4f6fd98013b5bf69bf63cc7944.zip
Add emitAssemblyMethod to TargetMachine
llvm-svn: 635
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Sparc/SparcInternals.h20
1 files changed, 11 insertions, 9 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index 1980c2e803a..ab01fd70329 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -441,7 +441,7 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = {
// numDelaySlots (in cycles)
// latency (in cycles)
// instr sched class (defined above)
- // instr class flags (defined in TargretMachine.h)
+ // instr class flags (defined in MachineInstrInfo.h)
{ "NOP", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG },
@@ -900,8 +900,6 @@ class UltraSparcRegInfo : public MachineRegInfo
MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
unsigned RegClassID) const ;
-
-
public:
@@ -996,7 +994,6 @@ class UltraSparcRegInfo : public MachineRegInfo
// given the unified register number, this gives the name
inline const string getUnifiedRegName(int reg) const {
-
if( reg < 32 )
return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) )
@@ -1728,16 +1725,21 @@ public:
UltraSparc();
virtual ~UltraSparc() {}
- virtual const MachineInstrInfo& getInstrInfo() const { return instrInfo; }
-
- virtual const MachineSchedInfo& getSchedInfo() const { return schedInfo; }
-
- virtual const MachineRegInfo& getRegInfo() const { return regInfo; }
+ virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
+ virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
+ virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
// compileMethod - For the sparc, we do instruction selection, followed by
// delay slot scheduling, then register allocation.
//
virtual bool compileMethod(Method *M);
+
+ //
+ // emitAssembly - Output assembly language code (a .s file) for the specified
+ // module. The specified module must have been compiled before this may be
+ // used.
+ //
+ virtual void emitAssembly(const Module *M, ostream &OutStr);
};
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