Fix that pesky floats in integer regs problem by assigning the f32 type to

the correct register class.  Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.

llvm-svn: 20857

1 files changed, 4 insertions, 8 deletions

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 7ec033afb86..fb00e46e6f6 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -44,7 +44,7 @@ namespace {
 
       // Set up the register classes.
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
-      addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
+      addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
       addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
       
       computeRegisterProperties();
@@ -322,13 +322,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
             // store only the non-fixed arguments in a vararg function.
             Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
                                          Args[i].first, PtrOff));
-            if (GPR_remaining > 0)
-              args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
-            if (GPR_remaining > 1) {
-              SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
-              PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-              args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
-            }
+            // FIXME: Need a way to communicate to the ISD::CALL select code
+            // that a particular argument is non-fixed so that we can load them
+            // into the correct GPR to shadow the FPR
           }
           args_to_use.push_back(Args[i].first);
           --FPR_remaining;