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authorAdam Nemet <anemet@apple.com>2014-03-07 23:56:28 +0000
committerAdam Nemet <anemet@apple.com>2014-03-07 23:56:28 +0000
commit5117f5dffc608eec512bfa89021f78678d8505c3 (patch)
treeaf526d681652e538248d45275018b33932b52287 /llvm/lib
parentc6553a83547648f726607c89a8824c8d6a9e32ae (diff)
downloadbcm5719-llvm-5117f5dffc608eec512bfa89021f78678d8505c3.tar.gz
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[DAGCombiner] Recognize another rotation idiom
This is the new idiom: x<<(y&31) | x>>((0-y)&31) which is recognized as: x ROTL (y&31) The change refines matchRotateSub. In Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1), if Pos is Pos' & (OpSize - 1) we can just use Pos' instead of Pos. llvm-svn: 203315
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 97885d4f3f8..f9388185b43 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3466,6 +3466,14 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
return 0;
SDValue NegOp1 = Neg.getOperand(1);
+ // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
+ // Pos'. The truncation is redundant for the purpose of the equality.
+ if (MaskLoBits &&
+ Pos.getOpcode() == ISD::AND &&
+ Pos.getOperand(1).getOpcode() == ISD::Constant &&
+ cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
+ Pos = Pos.getOperand(0);
+
// The condition we need is now:
//
// (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
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