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| author | Justin Holewinski <jholewinski@nvidia.com> | 2014-07-23 17:40:45 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2014-07-23 17:40:45 +0000 |
| commit | 511664dc7677cd45dc1e6f62e49a1fb0c7db0b11 (patch) | |
| tree | 1ded59d9f49c3e5ee23bee23f1c8948430d4fd03 /llvm/lib | |
| parent | e6b4ba1c41f35fccdd9dac4967cdd9bbc2074fb9 (diff) | |
| download | bcm5719-llvm-511664dc7677cd45dc1e6f62e49a1fb0c7db0b11.tar.gz bcm5719-llvm-511664dc7677cd45dc1e6f62e49a1fb0c7db0b11.zip | |
[NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled
With optimizations disabled, we disable the isel patterns for mul.wide; but we
were still generating MULWIDE ISD nodes. Now, we only try to generate MULWIDE
ISD nodes in DAGCombine if the optimization level is not zero.
llvm-svn: 213773
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 05bad16ddd8..d76b20a29eb 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -4213,8 +4213,7 @@ static SDValue PerformSHLCombine(SDNode *N, SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { - // FIXME: Get this from the DAG somehow - CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive; + CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel(); switch (N->getOpcode()) { default: break; case ISD::ADD: |
