diff options
| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-09-18 14:17:57 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-09-18 14:17:57 +0000 |
| commit | 4e6df159621fd578e7380732b3965dc9eab4bbf4 (patch) | |
| tree | 70b4bc3b8bf275fb0655448fa519a678e25460bb /llvm/lib | |
| parent | c0a758d8abcafa9f696b29bcf5eea44df9b96973 (diff) | |
| download | bcm5719-llvm-4e6df159621fd578e7380732b3965dc9eab4bbf4.tar.gz bcm5719-llvm-4e6df159621fd578e7380732b3965dc9eab4bbf4.zip | |
[ARM] Fix for indexed dot product instruction descriptions
The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:
vudot.u8 d16,d16,d18[0]
Differential Revision: https://reviews.llvm.org/D37968
llvm-svn: 313531
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 9c729bd2c9f..86c90efce2c 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -4710,7 +4710,7 @@ def VSDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b0, // Indexed dot product instructions: class DOTI<string opc, string dt, bit Q, bit U, RegisterClass Ty> : N3Vnp<0b11100, 0b10, 0b1101, Q, U, - (outs Ty:$Vd), (ins Ty:$Vn, DPR:$Vm, VectorIndex32:$lane), + (outs Ty:$Vd), (ins Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm, IIC_VDOTPROD, opc, dt, []> { bit lane; let Inst{5} = lane; |
