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| author | Dan Gohman <gohman@apple.com> | 2007-11-05 23:16:33 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2007-11-05 23:16:33 +0000 |
| commit | 4decbc50022c4f62b07cc245de8f1a912523b7ab (patch) | |
| tree | 149e1d5eebfa22614d0a731d417cdf2f96b7a8a8 /llvm/lib | |
| parent | fa0df55bdd807c103be0da2bc8a1dd86921f5860 (diff) | |
| download | bcm5719-llvm-4decbc50022c4f62b07cc245de8f1a912523b7ab.tar.gz bcm5719-llvm-4decbc50022c4f62b07cc245de8f1a912523b7ab.zip | |
Fix an abort in instcombine when folding creates a vector rem instruction.
llvm-svn: 43743
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index 6ebf42a96d8..c0ea28bd6e4 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -2622,6 +2622,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) { if (I.getType()->isInteger()) { APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { + // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set return BinaryOperator::createUDiv(Op0, Op1, I.getName()); } } @@ -2811,6 +2812,7 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) { Instruction *InstCombiner::visitSRem(BinaryOperator &I) { Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); + // Handle the integer rem common cases if (Instruction *common = commonIRemTransforms(I)) return common; @@ -2823,12 +2825,14 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) { return &I; } - // If the top bits of both operands are zero (i.e. we can prove they are + // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a urem. - APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); - if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { - // X srem Y -> X urem Y, iff X and Y don't have sign bit set - return BinaryOperator::createURem(Op0, Op1, I.getName()); + if (I.getType()->isInteger()) { + APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); + if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { + // X srem Y -> X urem Y, iff X and Y don't have sign bit set + return BinaryOperator::createURem(Op0, Op1, I.getName()); + } } return 0; |

