diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-15 01:40:18 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-15 01:40:18 +0000 |
| commit | 4bf01357e189e31b7c677de38835ce0909c9534d (patch) | |
| tree | 478a6ce14a152a81725df79672b9a0a3f2263799 /llvm/lib | |
| parent | 9511910e11705fe623c41ecd8b0f240a1581b16a (diff) | |
| download | bcm5719-llvm-4bf01357e189e31b7c677de38835ce0909c9534d.tar.gz bcm5719-llvm-4bf01357e189e31b7c677de38835ce0909c9534d.zip | |
Fit long lines into 80 cols via creative space elimination
llvm-svn: 16353
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 701c7daaa31..4262a9ffd70 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -36,10 +36,10 @@ let Namespace = "X86" in { def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>; // 8-bit registers - def AL : RegisterGroup<"AL", [AX, EAX]>; def CL : RegisterGroup<"CL", [CX, ECX]>; - def DL : RegisterGroup<"DL", [DX, EDX]>; def BL : RegisterGroup<"BL", [BX, EBX]>; - def AH : RegisterGroup<"AH", [AX, EAX]>; def CH : RegisterGroup<"CH", [CX, ECX]>; - def DH : RegisterGroup<"DH", [DX, EDX]>; def BH : RegisterGroup<"BH", [BX, EBX]>; + def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>; + def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>; + def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>; + def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>; // Pseudo Floating Point registers def FP0 : Register<"FP0">; def FP1 : Register<"FP1">; |
