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| author | Michael Zuckerman <Michael.zuckerman@intel.com> | 2016-12-18 14:29:00 +0000 |
|---|---|---|
| committer | Michael Zuckerman <Michael.zuckerman@intel.com> | 2016-12-18 14:29:00 +0000 |
| commit | 4b88a770efda1a69fd7b276231c9dd5014417a3d (patch) | |
| tree | 7772d10555883b0f99c05cece4b8d97ade70139c /llvm/lib | |
| parent | e940daf5329275e57a3bde6cba1ed2d345292764 (diff) | |
| download | bcm5719-llvm-4b88a770efda1a69fd7b276231c9dd5014417a3d.tar.gz bcm5719-llvm-4b88a770efda1a69fd7b276231c9dd5014417a3d.zip | |
[X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.
Commit on behalf of Gadi Haber
Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified.
The changed encodings are validated with XED.
Rviewers: delena, igorb
Differential revision: https://reviews.llvm.org/D27802
llvm-svn: 290065
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 69554ea0eb4..0fd95cdedd0 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6107,8 +6107,7 @@ multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, let Predicates = [HasAVX512] in { defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>, avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src, - OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>, - EVEX_V512, XD; + OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>, XD; } } @@ -6118,7 +6117,7 @@ multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, let Predicates = [HasAVX512] in { defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>, avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>, - EVEX_CD8<32, CD8VT1>, XS, EVEX_V512; + EVEX_CD8<32, CD8VT1>, XS; } } defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", |
