[CostModel][X86] Add SHLD/SHRD scalar funnel shift costs

The costs match the typical reg-reg cases - the RMW case can be a lot slower but we don't model that at this level

llvm-svn: 346683

1 files changed, 11 insertions, 2 deletions

diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index b8f6c540d15..6e25e701f3f 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1848,12 +1848,16 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
     { ISD::FSQRT,      MVT::v4f32,  56 }, // Pentium III from http://www.agner.org/
   };
   static const CostTblEntry X64CostTbl[] = { // 64-bit targets
-    { ISD::BITREVERSE, MVT::i64,    14 }
+    { ISD::BITREVERSE, MVT::i64,    14 },
+    { X86ISD::SHLD,    MVT::i64,     4 } 
   };
   static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
     { ISD::BITREVERSE, MVT::i32,    14 },
     { ISD::BITREVERSE, MVT::i16,    14 },
-    { ISD::BITREVERSE, MVT::i8,     11 }
+    { ISD::BITREVERSE, MVT::i8,     11 },
+    { X86ISD::SHLD,    MVT::i32,     4 },
+    { X86ISD::SHLD,    MVT::i16,     4 },
+    { X86ISD::SHLD,    MVT::i8,      4 }
   };
 
   unsigned ISD = ISD::DELETED_NODE;
@@ -1875,6 +1879,11 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
   case Intrinsic::cttz:
     ISD = ISD::CTTZ;
     break;
+  case Intrinsic::fshl:
+  case Intrinsic::fshr:
+    // SHRD has same costs so don't duplicate.
+    ISD = X86ISD::SHLD;
+    break;
   case Intrinsic::sqrt:
     ISD = ISD::FSQRT;
     break;