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authorJohnny Chen <johnny.chen@apple.com>2010-04-14 02:05:29 +0000
committerJohnny Chen <johnny.chen@apple.com>2010-04-14 02:05:29 +0000
commit48bbf4910eedfb248c26a39d03cacd50986910d0 (patch)
tree7453a6d04f5741afd239e2f60fb217ba68796ae8 /llvm/lib
parentb723860aacfd4a05cd0c2dd67c7c77d9385fde15 (diff)
downloadbcm5719-llvm-48bbf4910eedfb248c26a39d03cacd50986910d0.tar.gz
bcm5719-llvm-48bbf4910eedfb248c26a39d03cacd50986910d0.zip
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler just returns false, instead of assert, to indicate disassembly error. llvm-svn: 101205
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp18
1 files changed, 14 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index aedd22eb3e8..e26b7bd3563 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -15,6 +15,7 @@
#include "ARMDisassemblerCore.h"
#include "ARMAddressingModes.h"
+#include "llvm/Support/raw_ostream.h"
/// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
/// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
@@ -885,14 +886,19 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return false;
}
-static inline uint32_t getBFCInvMask(uint32_t insn) {
+static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
uint32_t lsb = slice(insn, 11, 7);
uint32_t msb = slice(insn, 20, 16);
uint32_t Val = 0;
- assert(lsb <= msb && "Encoding error: lsb > msb");
+ if (lsb > msb) {
+ errs() << "Encoding error: lsb > msb\n";
+ return false;
+ }
+
for (uint32_t i = lsb; i <= msb; ++i)
Val |= (1 << i);
- return ~Val;
+ mask = ~Val;
+ return true;
}
static inline bool SaturateOpcode(unsigned Opcode) {
@@ -982,7 +988,11 @@ static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0
: getRegisterEnum(ARM::GPRRegClassID,
decodeRm(insn))));
- MI.addOperand(MCOperand::CreateImm(getBFCInvMask(insn)));
+ uint32_t mask = 0;
+ if (!getBFCInvMask(insn, mask))
+ return false;
+
+ MI.addOperand(MCOperand::CreateImm(mask));
OpIdx += 2;
return true;
}
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