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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-16 17:16:11 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-16 17:16:11 +0000 |
| commit | 4893aff94ed2acbef2ff91592a423195baee47dc (patch) | |
| tree | 24b3f674b643839964be3d097564e0859bd3fe19 /llvm/lib | |
| parent | eabc0d0fd5fff7f2e6385b5b60d3fff5e9862b55 (diff) | |
| download | bcm5719-llvm-4893aff94ed2acbef2ff91592a423195baee47dc.tar.gz bcm5719-llvm-4893aff94ed2acbef2ff91592a423195baee47dc.zip | |
[mips] Enforce compact branch restrictions
Check both operands for use of the $zero register which cannot be used with
a compact branch instruction.
Reviewers: dsanders, vkalintris
Differential Review: https://reviews.llvm.org/D23547
llvm-svn: 278824
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.cpp | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index c317ecb91b2..aedb8a46c6f 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -426,14 +426,19 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest // Pick the zero form of the branch for readable assembly and for greater // branch distance in non-microMIPS mode. + // Additional MIPSR6 does not permit the use of register $zero for compact + // branches. // FIXME: Certain atomic sequences on mips64 generate 32bit references to // Mips::ZERO, which is incorrect. This test should be updated to use // Subtarget.getABI().GetZeroReg() when those atomic sequences and others // are fixed. - bool BranchWithZeroOperand = - (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() && - (I->getOperand(1).getReg() == Mips::ZERO || - I->getOperand(1).getReg() == Mips::ZERO_64)); + int ZeroOperandPosition = -1; + bool BranchWithZeroOperand = false; + if (I->isBranch() && !I->isPseudo()) { + auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo(); + ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI); + BranchWithZeroOperand = ZeroOperandPosition != -1; + } if (BranchWithZeroOperand) { switch (NewOpc) { @@ -476,17 +481,11 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, MIB.addImm(0); - } else if (BranchWithZeroOperand) { - // For MIPSR6 and microMIPS branches with an explicit zero operand, copy - // everything after the zero. - MIB.addOperand(I->getOperand(0)); - - for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) { - MIB.addOperand(I->getOperand(J)); - } } else { - // All other cases copy all other operands. for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { + if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J) + continue; + MIB.addOperand(I->getOperand(J)); } } |

