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| author | Changpeng Fang <changpeng.fang@gmail.com> | 2016-06-22 21:33:49 +0000 |
|---|---|---|
| committer | Changpeng Fang <changpeng.fang@gmail.com> | 2016-06-22 21:33:49 +0000 |
| commit | 47efe1f6db1020674418be247e7ff499362cc09b (patch) | |
| tree | 8b9b5c15257e794c7877483615f3e11b18bc95ac /llvm/lib | |
| parent | 9a519a099e232c618dd290c8b845bad28fda69df (diff) | |
| download | bcm5719-llvm-47efe1f6db1020674418be247e7ff499362cc09b.tar.gz bcm5719-llvm-47efe1f6db1020674418be247e7ff499362cc09b.zip | |
AMDGPU/SI: Define an intrinsic to expose ds_swizzle_b32
Reviewers: tstellarAMD, arsenm
Differential Revision: http://reviews.llvm.org/D21533
llvm-svn: 273496
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 6f7159cf366..814cbd3093d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -823,7 +823,11 @@ defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmps defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; + +let Uses = [EXEC], mayLoad =0, mayStore = 0, isConvergent = 1 in { defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; +} + let mayStore = 0 in { defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; @@ -2339,6 +2343,14 @@ def : Pat < >; //===----------------------------------------------------------------------===// +// DS_SWIZZLE Intrinsic Pattern. +//===----------------------------------------------------------------------===// +def : Pat < + (int_amdgcn_ds_swizzle i32:$src, imm:$offset16), + (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0)) +>; + +//===----------------------------------------------------------------------===// // SMRD Patterns //===----------------------------------------------------------------------===// |
