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| author | David Green <david.green@arm.com> | 2019-07-05 15:21:29 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-07-05 15:21:29 +0000 |
| commit | 47afdaa4872e8617734e50bcc99bab149bfb08f8 (patch) | |
| tree | 316525d067d06f3f214526340a59aa4f917da927 /llvm/lib | |
| parent | df173bf9bc811471d6f46ecab55aa30258fd7851 (diff) | |
| download | bcm5719-llvm-47afdaa4872e8617734e50bcc99bab149bfb08f8.tar.gz bcm5719-llvm-47afdaa4872e8617734e50bcc99bab149bfb08f8.zip | |
[ARM] MVE patterns for VMVN, VORR and VBIC
This add simple Q register forms of bitwise not instructions.
Differential Revision: https://reviews.llvm.org/D63983
llvm-svn: 365214
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrMVE.td | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index a9cfce311ed..e1882635c8b 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -1530,6 +1530,15 @@ def MVE_VMVN : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm), let Inst{0} = 0b0; } +let Predicates = [HasMVEInt] in { + def : Pat<(v16i8 (vnotq (v16i8 MQPR:$val1))), + (v16i8 (MVE_VMVN (v16i8 MQPR:$val1)))>; + def : Pat<(v8i16 (vnotq (v8i16 MQPR:$val1))), + (v8i16 (MVE_VMVN (v8i16 MQPR:$val1)))>; + def : Pat<(v4i32 (vnotq (v4i32 MQPR:$val1))), + (v4i32 (MVE_VMVN (v4i32 MQPR:$val1)))>; +} + class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28> : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), iname, "", "$Qd, $Qn, $Qm", ""> { @@ -1588,6 +1597,20 @@ let Predicates = [HasMVEInt] in { (v8i16 (MVE_VEOR (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>; def : Pat<(v4i32 (xor (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))), (v4i32 (MVE_VEOR (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>; + + def : Pat<(v16i8 (and (v16i8 MQPR:$val1), (vnotq MQPR:$val2))), + (v16i8 (MVE_VBIC (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; + def : Pat<(v8i16 (and (v8i16 MQPR:$val1), (vnotq MQPR:$val2))), + (v8i16 (MVE_VBIC (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>; + def : Pat<(v4i32 (and (v4i32 MQPR:$val1), (vnotq MQPR:$val2))), + (v4i32 (MVE_VBIC (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>; + + def : Pat<(v16i8 (or (v16i8 MQPR:$val1), (vnotq (v16i8 MQPR:$val2)))), + (v16i8 (MVE_VORN (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; + def : Pat<(v8i16 (or (v8i16 MQPR:$val1), (vnotq MQPR:$val2))), + (v8i16 (MVE_VORN (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>; + def : Pat<(v4i32 (or (v4i32 MQPR:$val1), (vnotq MQPR:$val2))), + (v4i32 (MVE_VORN (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>; } class MVE_bit_cmode<string iname, string suffix, bits<4> cmode, dag inOps> |
