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| author | Owen Anderson <resistor@mac.com> | 2010-12-10 22:46:47 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-12-10 22:46:47 +0000 |
| commit | 4743d7564075ca42b5f79b388961a80da9ea3b65 (patch) | |
| tree | b1562ed916aa41edbeb09adab1bf2bbf3fec35bc /llvm/lib | |
| parent | 006ab13b595b122227f8fff42fca52935788518f (diff) | |
| download | bcm5719-llvm-4743d7564075ca42b5f79b388961a80da9ea3b65.tar.gz bcm5719-llvm-4743d7564075ca42b5f79b388961a80da9ea3b65.zip | |
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
llvm-svn: 121587
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmBackend.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/ARMAsmBackend.cpp index 536d282d0ae..4555cd2082d 100644 --- a/llvm/lib/Target/ARM/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/ARMAsmBackend.cpp @@ -207,12 +207,12 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // Offset by 4 and don't encode the lower bit, which is always 0. return ((Value - 4) >> 1) & 0xff; case ARM::fixup_arm_pcrel_10: - Value = Value - 6; // ARM fixups offset by an additional word and don't + Value = Value - 4; // ARM fixups offset by an additional word and don't // need to adjust for the half-word ordering. // Fall through. case ARM::fixup_t2_pcrel_10: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. - Value = Value - 2; + Value = Value - 4; bool isAdd = true; if ((int64_t)Value < 0) { Value = -Value; diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 73b0874491d..c02d85bfd42 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -53,7 +53,8 @@ public: { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel | |
