diff options
| author | Evandro Menezes <e.menezes@samsung.com> | 2017-11-20 19:11:56 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2017-11-20 19:11:56 +0000 |
| commit | 46f672b759f18b12e06e5eabc307e62a1ddaea55 (patch) | |
| tree | aea838f9615e5205ac3aeadacb41fbddea21b09f /llvm/lib | |
| parent | 746edea0ae359b888e272e6209602e9e86575794 (diff) | |
| download | bcm5719-llvm-46f672b759f18b12e06e5eabc307e62a1ddaea55.tar.gz bcm5719-llvm-46f672b759f18b12e06e5eabc307e62a1ddaea55.zip | |
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of test and branch.
llvm-svn: 318685
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedM1.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedM1.td b/llvm/lib/Target/AArch64/AArch64SchedM1.td index 4f35f088207..096f1e5c455 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedM1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedM1.td @@ -84,6 +84,9 @@ def M1WriteAC : SchedWriteRes<[M1UnitALU, M1UnitALU, M1UnitC]> { let Latency = 2; let NumMicroOps = 3; } +def M1WriteAD : SchedWriteRes<[M1UnitALU, + M1UnitC]> { let Latency = 2; + let NumMicroOps = 2; } def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteA1]>, SchedVar<NoSchedPred, [M1WriteAA]>]>; def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; } @@ -429,8 +432,7 @@ def : InstRW<[M1WriteB1], (instrs Bcc)>; def : InstRW<[M1WriteA1], (instrs BL)>; def : InstRW<[M1WriteBX], (instrs BLR)>; def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>; -def : InstRW<[M1WriteC1, - M1WriteA2], (instregex "^TBN?Z[WX]")>; +def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>; // Arithmetic and logical integer instructions. def : InstRW<[M1WriteA1], (instrs COPY)>; |
