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author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 16:58:27 +0000 |
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committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 16:58:27 +0000 |
commit | 46c05fc861c49b82e049aefd9799bc39edb2b768 (patch) | |
tree | 70cebf0c6a616f5ed41118e1f9a7e388bf32d2ea /llvm/lib | |
parent | 07994ec39b5242be73c420b5edc581536ad150cd (diff) | |
download | bcm5719-llvm-46c05fc861c49b82e049aefd9799bc39edb2b768.tar.gz bcm5719-llvm-46c05fc861c49b82e049aefd9799bc39edb2b768.zip |
[GlobalISel] Remove types on selected insts instead of using LLT().
LLT() has a particular meaning: it's one invalid type. But we really
want selected instructions to have no type whatsoever.
Also verify that types don't linger after ISel, and enable the verifier
on the AArch64 select test.
llvm-svn: 277001
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 6 | ||||
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 10 | ||||
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 2 |
3 files changed, 17 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index ac5ce811f3a..ca3799db1ed 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -716,6 +716,8 @@ void MachineInstr::setType(LLT Ty, unsigned Idx) {} LLT MachineInstr::getType(unsigned Idx) const { return LLT{}; } +void MachineInstr::removeTypes() {} + #else unsigned MachineInstr::getNumTypes() const { return Tys.size(); } @@ -728,6 +730,10 @@ void MachineInstr::setType(LLT Ty, unsigned Idx) { } LLT MachineInstr::getType(unsigned Idx) const { return Tys[Idx]; } + +void MachineInstr::removeTypes() { + Tys.clear(); +} #endif // LLVM_BUILD_GLOBAL_ISEL /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 23a89f865c1..8f8013adc98 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -879,6 +879,16 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { } } + // Check types. + const unsigned NumTypes = MI->getNumTypes(); + if (isPreISelGenericOpcode(MCID.getOpcode())) { + if (NumTypes == 0) + report("Generic instruction must have a type", MI); + } else { + if (NumTypes != 0) + report("Non-generic instruction cannot have a type", MI); + } + StringRef ErrorInfo; if (!TII->verifyInstruction(*MI, ErrorInfo)) report(ErrorInfo.data(), MI); diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 6899950c263..26b574af464 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -150,7 +150,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { I.setDesc(TII.get(NewOpc)); // FIXME: Should the type be always reset in setDesc? - I.setType(LLT()); + I.removeTypes(); // Now that we selected an opcode, we need to constrain the register // operands to use appropriate classes. |