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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-08 19:09:13 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-08 19:09:13 +0000 |
| commit | 461ed08fbdf486cf2905cec6dc4b901e5d46d3b1 (patch) | |
| tree | 259efc20798b7f14c1c3381eae53e18bab2e5b5a /llvm/lib | |
| parent | 57acd0ad01fe8ff60baf767ac6fcaa9dc98e798a (diff) | |
| download | bcm5719-llvm-461ed08fbdf486cf2905cec6dc4b901e5d46d3b1.tar.gz bcm5719-llvm-461ed08fbdf486cf2905cec6dc4b901e5d46d3b1.zip | |
AMDGPU: Start using !con operator
We have a lot of operand definition work essentially producing
every valid permutation of operands to workaround builiding
operand lists based on the instruction features. Apparently tablegen
already has a mostly undocumented operator to concat dags which
simplies this.
Convert one simple place to use this. The BUF instruction definitions
have much more complicated logic that can be totally rewritten now.
llvm-svn: 312822
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/FLATInstructions.td | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 9a9d051aced..9ba356add1e 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -128,13 +128,12 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass, bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo< opName, (outs regClass:$vdst), - !if(EnableSaddr, - !if(HasSignedOffset, - (ins VReg_64:$vaddr, SReg_64:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc), - (ins VReg_64:$vaddr, SReg_64:$saddr, offset_u12:$offset, GLC:$glc, slc:$slc)), - !if(HasSignedOffset, - (ins VReg_64:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc), - (ins VReg_64:$vaddr, offset_u12:$offset, GLC:$glc, slc:$slc))), + !con( + !con( + !con((ins VReg_64:$vaddr), + !if(EnableSaddr, (ins SReg_64:$saddr), (ins))), + (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)), + (ins GLC:$glc, slc:$slc)), " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> { let has_data = 0; let mayLoad = 1; @@ -148,13 +147,12 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass, bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo< opName, (outs), - !if(EnableSaddr, - !if(HasSignedOffset, - (ins VReg_64:$vaddr, vdataClass:$vdata, SReg_64:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc), - (ins VReg_64:$vaddr, vdataClass:$vdata, SReg_64:$saddr, offset_u12:$offset, GLC:$glc, slc:$slc)), - !if(HasSignedOffset, - (ins VReg_64:$vaddr, vdataClass:$vdata, offset_s13:$offset, GLC:$glc, slc:$slc), - (ins VReg_64:$vaddr, vdataClass:$vdata, offset_u12:$offset, GLC:$glc, slc:$slc))), + !con( + !con( + !con((ins VReg_64:$vaddr, vdataClass:$vdata), + !if(EnableSaddr, (ins SReg_64:$saddr), (ins))), + (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)), + (ins GLC:$glc, slc:$slc)), " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> { let mayLoad = 0; let mayStore = 1; |
