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| author | Jiangning Liu <jiangning.liu@arm.com> | 2014-07-24 01:29:59 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2014-07-24 01:29:59 +0000 |
| commit | 451f30e89f882e796cbba744fc4f340b7ddbf43f (patch) | |
| tree | a539e0ce7cb525b8c17f76d144b7c955dc8638fc /llvm/lib | |
| parent | 933cccf3fa81a928a026a88483d30d202c6b048e (diff) | |
| download | bcm5719-llvm-451f30e89f882e796cbba744fc4f340b7ddbf43f.tar.gz bcm5719-llvm-451f30e89f882e796cbba744fc4f340b7ddbf43f.zip | |
[AArch64] Disable some optimization cases for type conversion from sint to fp, because those optimization cases are micro-architecture dependent and only make sense for Cyclone. A new predicate Cyclone is introduced in .td file.
llvm-svn: 213827
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 0ba069e99a8..1f84a7f0e6d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -24,6 +24,7 @@ def HasCRC : Predicate<"Subtarget->hasCRC()">, AssemblerPredicate<"FeatureCRC", "crc">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; +def IsCyclone : Predicate<"Subtarget->isCyclone()">; //===----------------------------------------------------------------------===// // AArch64-specific DAG Nodes. @@ -4386,7 +4387,7 @@ class SExtLoadi8CVTf32Pat<dag addrmode, dag INST> 0), dsub)), 0), - ssub)))>, Requires<[NotForCodeSize]>; + ssub)))>, Requires<[NotForCodeSize, IsCyclone]>; def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; @@ -4439,8 +4440,8 @@ class SExtLoadi16CVTf64Pat<dag addrmode, dag INST> 0), dsub)), 0), - dsub)))>, Requires<[NotForCodeSize]>; - + dsub)))>, Requires<[NotForCodeSize, IsCyclone]>; + def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), |
