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| author | Chris Lattner <sabre@nondot.org> | 2006-05-05 21:35:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-05 21:35:18 +0000 |
| commit | 44a73e9fa581dcfbaa8e9f39f2709ac8521d4ea7 (patch) | |
| tree | d5ae85cc4b99df018ab157c4cdbc312e05f71219 /llvm/lib | |
| parent | 3d26577396f589141293a56d50235ea8ca2b3260 (diff) | |
| download | bcm5719-llvm-44a73e9fa581dcfbaa8e9f39f2709ac8521d4ea7.tar.gz bcm5719-llvm-44a73e9fa581dcfbaa8e9f39f2709ac8521d4ea7.zip | |
Teach the code generator to use cvtss2sd as extload f32 -> f64
llvm-svn: 28131
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 2 |
2 files changed, 1 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7186fe51afc..0ec11ac98f6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -207,10 +207,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, X86::FR32RegisterClass); addRegisterClass(MVT::f64, X86::FR64RegisterClass); - // SSE has no load+extend ops - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); - // Use ANDPD to simulate FABS. setOperationAction(ISD::FABS , MVT::f64, Custom); setOperationAction(ISD::FABS , MVT::f32, Custom); diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 6b799945b9d..3c1db671462 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -526,7 +526,7 @@ def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), Requires<[HasSSE2]>; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, + [(set FR64:$dst, (extload addr:$src, f32))]>, XS, Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). |
