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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-23 18:30:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-23 18:30:57 +0000 |
| commit | 4364fef82f06ebffd6dda0802a0b22126ae52c77 (patch) | |
| tree | 5b7e00aa4a04b640bc574d744eed564672315f8c /llvm/lib | |
| parent | 9d28cf5609691e323a4bae257f1ef49968aa4e83 (diff) | |
| download | bcm5719-llvm-4364fef82f06ebffd6dda0802a0b22126ae52c77.tar.gz bcm5719-llvm-4364fef82f06ebffd6dda0802a0b22126ae52c77.zip | |
Fix typo
llvm-svn: 218324
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index b79286f810d..14d04ff9b1f 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -1146,9 +1146,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, // Handle non-register types that are treated like immediates. assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI()); - if (!DefinedRC) - // This opperand expects an immediate + if (!DefinedRC) { + // This operand expects an immediate. return true; + } return RI.regClassCanUseImmediate(DefinedRC); } |
