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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-02-05 15:24:47 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-02-05 15:24:47 +0000 |
| commit | 433b1c3aaefc74edcf98bb59007de3e992d22cd6 (patch) | |
| tree | 32d97e9322873fccdc35724f54e6a433bb9319d2 /llvm/lib | |
| parent | f8d662aa4b554ba903be9b19620cf9621fd99525 (diff) | |
| download | bcm5719-llvm-433b1c3aaefc74edcf98bb59007de3e992d22cd6.tar.gz bcm5719-llvm-433b1c3aaefc74edcf98bb59007de3e992d22cd6.zip | |
[PowerPC] Implement the vclz instructions for PWR8
Patch by Kit Barton.
Add the vector count leading zeros instruction for byte, halfword,
word, and doubleword sizes. This is a fairly straightforward addition
after the changes made for vpopcnt:
1. Add the correct definitions for the various instructions in
PPCInstrAltivec.td
2. Make the CTLZ operation legal on vector types when using P8Altivec
in PPCISelLowering.cpp
Test Plan
Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the
instructions are being generated when the CTLZ operation is used in
LLVM.
Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s
and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively.
llvm-svn: 228301
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 15 |
2 files changed, 22 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index dd3362ff353..b98c9e1b067 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -401,11 +401,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::ADD , VT, Legal); setOperationAction(ISD::SUB , VT, Legal); - // Vector popcnt instructions introduced in P8 - if (Subtarget.hasP8Altivec()) + // Vector instructions introduced in P8 + if (Subtarget.hasP8Altivec()) { setOperationAction(ISD::CTPOP, VT, Legal); - else + setOperationAction(ISD::CTLZ, VT, Legal); + } + else { setOperationAction(ISD::CTPOP, VT, Expand); + setOperationAction(ISD::CTLZ, VT, Expand); + } // We promote all shuffles to v16i8. setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); @@ -461,7 +465,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); setOperationAction(ISD::FPOW, VT, Expand); setOperationAction(ISD::BSWAP, VT, Expand); - setOperationAction(ISD::CTLZ, VT, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); setOperationAction(ISD::CTTZ, VT, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 5641b536569..9379bad7317 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -940,6 +940,21 @@ def : Pat<(v4f32 (fnearbyint v4f32:$vA)), def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; let Predicates = [HasP8Altivec] in { + +// Count Leading Zeros +def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), + "vclzb $vD, $vB", IIC_VecGeneral, + [(set v16i8:$vD, (ctlz v16i8:$vB))]>; +def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), + "vclzh $vD, $vB", IIC_VecGeneral, + [(set v8i16:$vD, (ctlz v8i16:$vB))]>; +def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), + "vclzw $vD, $vB", IIC_VecGeneral, + [(set v4i32:$vD, (ctlz v4i32:$vB))]>; +def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), + "vclzd $vD, $vB", IIC_VecGeneral, + [(set v2i64:$vD, (ctlz v2i64:$vB))]>; + // Population Count def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), "vpopcntb $vD, $vB", IIC_VecGeneral, |
