diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-10-28 23:51:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-10-28 23:51:35 +0000 |
| commit | 42aa87143d0ce47ddcba5eab82c4a66b76b7b2dd (patch) | |
| tree | 7be5d10cb24f8565bb5f218d56a4034e1ef3e58a /llvm/lib | |
| parent | 8164f3923e64b1d9ee5479dda6c600349e896640 (diff) | |
| download | bcm5719-llvm-42aa87143d0ce47ddcba5eab82c4a66b76b7b2dd.tar.gz bcm5719-llvm-42aa87143d0ce47ddcba5eab82c4a66b76b7b2dd.zip | |
[X86] Recognize constant splats in LowerFCOPYSIGN.
llvm-svn: 345484
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 060b36c868e..f2c5040b89e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18060,7 +18060,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // TODO: If we had general constant folding for FP logic ops, this check // wouldn't be necessary. SDValue MagBits; - if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Mag)) { + if (ConstantFPSDNode *Op0CN = isConstOrConstSplatFP(Mag)) { APFloat APF = Op0CN->getValueAPF(); APF.clearSign(); MagBits = DAG.getConstantFP(APF, dl, LogicVT); |
