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| author | Craig Topper <craig.topper@intel.com> | 2018-04-30 06:21:21 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-30 06:21:21 +0000 |
| commit | 429ae3d775257a6550e96ee7ac5a8b2400c97793 (patch) | |
| tree | da59c53a630b917773a158e091e53fe0c20c7a8a /llvm/lib | |
| parent | ebc7de07ee2ba67fff24470a74d39a4258c38166 (diff) | |
| download | bcm5719-llvm-429ae3d775257a6550e96ee7ac5a8b2400c97793.tar.gz bcm5719-llvm-429ae3d775257a6550e96ee7ac5a8b2400c97793.zip | |
[X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.
This patch hides the Not64BitMode from the table so there is no conflict anymore.
llvm-svn: 331158
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrControl.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index 966f85ae28e..979419a6e3c 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -167,7 +167,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; } - let Predicates = [Not64BitMode] in { + let Predicates = [Not64BitMode], AsmVariantName = "att" in { def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "ljmp{w}\t$seg, $off", []>, @@ -244,7 +244,7 @@ let isCall = 1 in Sched<[WriteJumpLd]>, NOTRACK; } - let Predicates = [Not64BitMode] in { + let Predicates = [Not64BitMode], AsmVariantName = "att" in { def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "lcall{w}\t$seg, $off", []>, |
